Related Papers
ACM Transactions on Design Automation of Electronic Systems
A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation
Rabin Acharya
Artificial intelligence (AI) and machine learning (ML) techniques have been increasingly used in several fields to improve performance and the level of automation. In recent years, this use has exponentially increased due to the advancement of high-performance computing and the ever increasing size of data. One of such fields is that of hardware design—specifically the design of digital and analog integrated circuits, where AI/ ML techniques have been extensively used to address ever-increasing design complexity, aggressive time to market, and the growing number of ubiquitous interconnected devices. However, the security concerns and issues related to integrated circuit design have been highly overlooked. In this article, we summarize the state-of-the-art in AI/ML for circuit design/optimization, security and engineering challenges, research in security-aware computer-aided design/electronic design automation, and future research directions and needs for using AI/ML for security-awa...
Integration
Defense-in-depth: A recipe for logic locking to prevail
2020 •
Sazadur Rahman
Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
Post-layout Security Evaluation Methodology Against Probing Attacks
2021 •
sofiane takarabt
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)
Cryptographically secure shields
2014 •
Yves Mathieu
ACM Journal on Emerging Technologies in Computing Systems
A Survey on Chip to System Reverse Engineering
2016 •
John Chandy
The reverse engineering (RE) of electronic chips and systems can be used with honest and dishonest intentions. To inhibit RE for those with dishonest intentions (e.g., piracy and counterfeiting), it is important that the community is aware of the state-of-the-art capabilities available to attackers today. In this article, we will be presenting a survey of RE and anti-RE techniques on the chip, board, and system levels. We also highlight the current challenges and limitations of anti-RE and the research needed to overcome them. This survey should be of interest to both governmental and industrial bodies whose critical systems and intellectual property (IP) require protection from foreign enemies and counterfeiters who possess advanced RE capabilities.
Proceedings of the International Conference on Omni-Layer Intelligent Systems
Protect Your Chip Design Intellectual Property
Ozgur Sinanoglu
ACM Transactions on Design Automation of Electronic Systems
IP Protection and Supply Chain Security through Logic Obfuscation
Saverio Fazzari
The globalization of the semiconductor supply chain introduces ever-increasing security and privacy risks. Two major concerns are IP theft through reverse engineering and malicious modification of the design. The latter concern in part relies on successful reverse engineering of the design as well. IC camouflaging and logic locking are two of the techniques under research that can thwart reverse engineering by end-users or foundries. However, developing low overhead locking/camouflaging schemes that can resist the ever-evolving state-of-the-art attacks has been a challenge for several years. This article provides a comprehensive review of the state of the art with respect to locking/camouflaging techniques. We start by defining a systematic threat model for these techniques and discuss how various real-world scenarios relate to each threat model. We then discuss the evolution of generic algorithmic attacks under each threat model eventually leading to the strongest existing attacks....
IEEE Transactions on Computers
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks
2000 •
Guido Bertoni, Sylvain Guilley
AbstractLogic styles with constant power consumption are promising solutions to counteract side-channel attacks on sensitive cryptographic devices. Recently, one vulnerability has been identified in a standard-cell based power-constant logic called WDDL. Another logic, ...
IEEE Transactions on Computers
Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics
2000 •
Florent Flament
Using Supply Voltage Metal Layers as Low Cost Means to Hinder Several Types of Physical Attacks
SDIWC Organization
In this paper, we describe the idea of using the metallization layers used for supplying ICs with VDD and GND as a low-cost countermeasure for semi-invasive front-side attacks. The core of our idea is to realize both supply voltages – GND and VDD – no longer fixed on metal one but to shift them up in different top metal layers and to implement it both as metal plane. This helps to prevent semi invasive attacks that require an optical access to the transistor level while the device is fully functional. An additional countermeasure effect may be hindering of EMA, PA and microprobing. Early experiments with a simple 3x3 multiplier show that our idea can be used with standard layout tools such as encounter from synopsis.
